x86-64 Instructions Set

CPU instructions

The general-purpose instructions perform basic data movement, arithmetic, logic, program flow, and string operations which programmers commonly use to write application and system software to run on Intel 64 and IA-32 processors. They operate on data contained in memory, in the general-purpose registers (EAX, EBX, ECX, EDX, EDI, ESI, EBP, and ESP) and in the EFLAGS register. They also operate on address information contained in memory, the general-purpose registers, and the segment registers (CS, DS, SS, ES, FS, and GS).

FPU instructions

The x87‭ ‬FPU instructions are executed by the so-called "math coprocessor"‬.‭ ‬These instructions operate on floating-point,‭ integer,‭ ‬and binary-coded decimal (BCD) ‬operands.‭ The main purpose of these instructions are to perform floating-point arithmetic.‭ ‬But nowadays we have SIMD instructions that are much faster than FPU.‭ ‬So,‭ please,‭ don't use the FPU in newly written code,‭ because it usage is marked as outdated in Linux ‬64‭ ‬ABI.‭ ‬Use SIMD instead.

SIMD instructions

Beginning with the Pentium II and Pentium with Intel MMX technology processor families,‭ many extensions have been introduced into the Intel ‬64‭ ‬and IA-32‭ ‬architectures to perform single-instruction multiple-data (‬SIMD‭) ‬operations.‭ These extensions include the MMX technology,‭ ‬SSE,‭ ‬SSE2,‭ ‬SSE3,‭ SSE4, AVX, AVX2 and AVX512 extensions.‭ Each of these extensions provide a group of instructions that perform SIMD operations on packed integer and/or packed floating-point data elements.

AMX instructions

Intel Advanced Matrix Extensions (Intel AMX), are extensions to the x86 instruction set architecture (ISA) for microprocessors from Intel designed to work on matrices to accelerate artificial intelligence (AI) and machine learning (ML) workloads.

MPX instructions

Memory Protection Extensions (MPX) is a new capability introduced into Intel Architecture. MPX can increase the robustness of software when it is used in conjunction with compiler changes to check memory references, for those references whose compile-time normal intentions are usurped at runtime due to buffer overflow or underflow. Two of the most important goals of MPX are to provide this capability at low performance overhead for newly compiled code, and to provide compatibility mechanisms with legacy software components. A direct benefit MPX provides is hardening software against malicious attacks designed to cause or exploit buffer overruns.

SGX instructions

Intel Software Guard Extensions (SGX) provide two sets of instruction leaf functions to enable application software to instantiate a protected container, referred to as an enclave. The enclave instructions are organized as leaf functions under two instruction mnemonics: ENCLS (ring 0) and ENCLU (ring 3).

SMX instructions

Safer Mode Extensions (‬SMX‭) provides a programming interface for system software to establish a measured environment within the platform to support trust decisions by end users.‭ ‬SMX functionality is provided in an Intel ‬64‭ processor through the GETSEC instruction via leaf functions.

TSX instructions

Transactional Synchronization Extensions (TSX) allow the processor to determine dynamically whether threads need to serialize through lock-protected critical sections, and to perform serialization only when required. This lets the hardware expose and exploit concurrency hidden in an application due to dynamically unnecessary synchronization through a technique known as lock elision.

VMX instructions

VM extension allows multiple operating systems to share simultaneously x86‭ processor resources in a safe and efficient manner.‭ An Intel platform with VMX can function as multiple virtual systems or virtual machines‬.‭ Each virtual machine can run operating systems and applications in separate partitions.‭ ‬VMX also provides programming interface for a new layer of system software,‭ called the Virtual Machine Monitor (‬VMM‭), used to manage the operation of virtual machines.